Personal computer systems generally include one or more local buses that permit peripheral devices to be connected to the computer system""s microprocessor. One such local bus is the PCI (Peripheral Component Interconnect) bus. A design concern associated with virtually any local bus architecture is the maximum rate of data transfer, or throughput, that can be achieved on the bus. The PCI bus provides substantial improvements over its predecessors in terms of data throughput. However, certain applications require even greater throughput than PCI can provide, particularly video and 3-D graphics applications.
Audio, video, and graphics applications are typically supported by peripheral devices known as xe2x80x9cadaptersxe2x80x9d or xe2x80x9cacceleratorsxe2x80x9d, that can be coupled to a local bus in a computer system. One way to reduce throughput requirements is to provide more local memory on the adapter. This solution reduces the amount of data that must be communicated over the bus and thus enhances the performance of the device. A disadvantage of this solution, however, is that many of these adapters use a type of memory that is expensive.
In contrast, the system memory in a computer system generally includes much more memory than these adapters can provide and tends to be easier to upgrade. The Accelerated Graphics Port (xe2x80x9cAGPxe2x80x9d) enables audio, video, or graphics adapters to more effectively make use of system memory and thereby reduce the amount of local memory that is required. In particular, AGP provides a high-throughput, component-level interconnect through which peripheral devices, such as audio, video, or graphics adapters, can access system memory.
While AGP has effectively increased the memory space available to adapters by allowing them to access system memory, there is a continuing need to enable AGP compliant masters to access information as quickly as possible.
In at least some embodiments, speed and efficiency may be improved by allowing an interface, such as AGP, to selectively write data directly to a peripheral device, such as a graphics accelerator at more than one data transfer rate. For example, write transactions to the graphics accelerator could proceed at higher rates associated with the interface or a lower rate associated with a bus connected to the interface.
In accordance with one aspect of the present invention, an interface between a system memory controller and a peripheral device. The interface includes an element adapted to selectively write data directly to the peripheral device at one of at least two rates. A selection device selects the rate at which data is written directly to the peripheral device.
In accordance with another aspect of the present invention, a method of transferring data between an interface, a system memory controller and a peripheral device includes selecting between at least two data transfer rates to the peripheral device. The data is transferred from the interface to the peripheral device at the selected rate.
In accordance with still another aspect of the present invention, an interface between a system memory controller and a graphics accelerator includes a connection for enabling the interface to connect to a system memory controller, a processor and a graphics accelerator. A device, communicating with the connection, is arranged to enable the interface to write directly to the graphics accelerator at a selected one of at least two data transfer rates.
In accordance with yet another aspect of the present invention, a method for transferring data between an interface, a system memory controller and a graphics accelerator includes determining whether the graphics accelerator can accept a given write transaction. Data is written from the interface directly to the graphics accelerator if the graphics accelerator can accept the transaction.
In accordance with but another aspect of the present invention, a computer system includes a processor, a system memory controller and a peripheral device. The interface has ports for connecting to the system memory controller, the processor, and the peripheral device. The system is adapted to selectively write data directly to the peripheral device at one of at least two data transfer rates.